PIC16F737-I/SP【PDF 126/231 页】IC PIC MCU FLASH 4KX14 28DIP

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Sheet目录3841

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2009 Microchip Technology Inc.

DS39636D-page 217

PIC18F2X1X/4X1X

The value in the ADRESH:ADRESL registers is not

modified for a Power-on Reset. The ADRESH:ADRESL

registers will contain unknown data after a Power-on

Reset.

After the A/D module has been configured as desired,

the selected channel must be acquired before the con-

version is started. The analog input channels must

have their corresponding TRIS bits selected as an

input. To determine acquisition time, see Section 18.1

“A/D Acquisition Requirements”. After this acquisi-

tion time has elapsed, the A/D conversion can be

started. An acquisition time can be programmed to

occur between setting the GO/DONE bit and the actual

start of the conversion.

To perform an A/D conversion, do the following steps:

Configure the A/D module:

Configure analog pins, voltage reference and

digital I/O (ADCON1)

Select A/D input channel (ADCON0)

Select A/D acquisition time (ADCON2)

Select A/D conversion clock (ADCON2)

Turn on A/D module (ADCON0)

Configure A/D interrupt (if desired):

Clear ADIF bit

Set ADIE bit

Set GIE bit

Wait the required acquisition time (if required).

Start conversion:

Set GO/DONE bit (ADCON0 register)

Wait for A/D conversion to complete, by either:

Polling for the GO/DONE bit to be cleared

Waiting for the A/D interrupt

Read A/D Result registers (ADRESH:ADRESL);

clear bit ADIF, if required.

For next conversion, go to step 1 or step 2, as

required. The A/D conversion time per bit is

defined as TAD. A minimum wait of 2 TAD is

required before the next acquisition starts.

FIGURE 18-2:

A/D TRANSFER FUNCTION

FIGURE 18-3:

ANALOG INPUT MODEL

Dig

ita

lCo

utp

3FEh

003h

002h

001h

000h

0.5

1.5

2.5

022

22.5

Analog Input Voltage

3FFh

023

23.5

VAIN

CPIN

ANx

5 pF

VT = 0.6V

ILEAKAGE

RIC

≤ 1k

Sampling

Switch

RSS

CHOLD = 25 pF

VSS

VDD

± 100 nA

Legend: CPIN

ILEAKAGE

RIC

CHOLD

= input capacitance

= threshold voltage

= leakage current at the pin due to

= interconnect resistance

= sampling switch

= sample/hold capacitance (from DAC)

various junctions

= sampling switch resistance

RSS

VDD

Sampling Switch

Ω)

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